Wp 2.4: a 12b 5msl.s Two-step Cmos Aid Converter*
نویسندگان
چکیده
The ADC architecture and timing diagram are shown in Figure 1. The converter consists of a 7b coarse flash stage, a 7b digital-to-analog converter (DAC), a subtractor. and a 6b fine flash stage. One-of-n decoders and ROhIs are used to convert the thermometer code outputs ofthe two flash stages to binarydata, that is thencorrecteddigitally to produce the final output. One bit ofredundancy. or overlap, is utilized in this architecture to enable the second stage to correct for errors made in the first stage, thereby relaxing the performance required of the first-stage comparators. With the present design, an external sample-and-hold must be used in order t o digitize high-frequency analog inputs.
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